Archive for June, 2006

FPGA land – from software to hardware

Thursday, June 22nd, 2006

One difficulty that presents itself is the software mindset. I’m a software developer myself, so I know a lot of the techniques of the software trade. But when I work with Verilog or VHDL, I adopt a completely different point of view.

With software, you view tasks in terms of sequence, repetition, and selection (choice). The predominant mode of thought is sequential. Parallelism or concurrency is handled primarily by the use of multitasking techniques. To a limited extent, parallelism can also be attained through vectorization.

With hardware, I view the tasks in terms of connections, conditions, and updates. All of the components of the hardware work simultaneously – in parallel. Serialization or sequencing is handled by state machine techniques. State machines can be as simple as counters, but can be more elaborate.