tk's bits

This design simply runs a wire through the FPGA from one of the push buttons to one of the LED’s. Just one little assignment between two port signals does the trick. Push the button, and the LED lights up. Release the button, and the LED turns off.

All you have to do is figure out how to run the software tools, how to assign the signals to the right pins (via a UCF file), and how to configure the FPGA. (That’s right, they don’t want to call it “programming.”)

My original configuration method was to generate a PROM file (MCS) from the bit file, and then to program the Flash using iMPACT, Digilent’s parallel JTAG cable, and the MCS file. I’ve now obtained a USB-JTAG cable from Digilent, and download the BIT file directly to the FPGA using Digilent’s Adept ExPort utility.

My current setup automatically generates IBUF’s and OBUF’s automatically for top level signals. You can ensure this by highlighting Synthesis in the Processes window, then selecting Process from the menu bar, then selecting Properties…, then selecting Xilinx Specific Options. If the “Add I/O Buffers” option is checked, IBUF’s and OBUF’s will be automatically added to your design.

It’s also good to check the startup settings. First highlight Generate Programming File, and then select Process from the menu bar, followed by selecting Properties…, then Startup Options. The “FPGA Start-Up Clock” option can be set to CCLK if programming the Flash, or to JTAG Clock if downloading directly to the FPGA.

The following is the VHDL code…

-- BTNLD - Button to LED (LDn)
--
-- This is a simple wiring from a push button switch to
-- an LED.
--
-- Purpose: An introduction to all the little details of
--          getting a design built (synthesized) and then
--          downloading it to the FPGA board.

-- The following library and use lines are generated by
-- Xilinx software. Most designs will use the arithmetic
-- capabilities provided by these directives.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BTNLD is
    Port ( BTNIN : in std_logic;
           LEDOUT : out std_logic);
end BTNLD;

architecture Behavioral of BTNLD is
begin

  LEDOUT <= BTNIN;

end Behavioral;

The following is the Verilog code

// BTNLD - Button to LED (LDn)
//
// This is a simple wiring from a push button switch to
// an LED.
//
// Note: input and output ports are in Verilog 2001 syntax.
//
// Purpose: An introduction to all the little details of
//          getting a design built (synthesized) and then
//          downloading it to the FPGA board.

module BTNLD (
  input  BTNIN,
  output LEDOUT
  );

  assign LEDOUT = BTNIN;

endmodule

To control the pinout, Xilinx software uses a UCF file. It’s just a text file, and the above code only needs the following text in the UCF file…

# Signal BTNIN assigned to pin M13
# Signal LEDOUT assigned to pin K12
NET "BTNIN"  LOC = "M13" | IOSTANDARD = LVTTL ;
NET "LEDOUT"  LOC = "K12" | IOSTANDARD = LVTTL ;