tk's bits

This design implements a register. There are two inputs, clk and din, and one output, dout. The clk signal is connected to a push button, the din signal is connected to a slide switch, and the dout signal is connected to an LED.

You can flip the slide switch any number of times, but the LED won’t change state. Press the push button, and it will set the LED on or off depending on the position of the slide switch.

If you’re an assembly language programmer, you’re aware of the notion of registers as data holders. In FPGA terminology, we go a little further – the data in a register is stable until a specific signal, known as a clock, changes. When the clock changes, the internal data is updated with the value present on the register’s input.

If you’re strictly a software person, reread that last sentence. There is no need to “move” data from one location to another. Data is always present on the input. A useful register also has output. The same truth holds here – data is always present on the output. We are talking about wiring here. Like house wiring, the data (like the mains voltage) is always present. Another way to describe how a register works is to say, ”the clock signal is used to capture the input data.”

In Verilog and VHDL, we use assignments for several purposes.

In the case of some usages, the assignment represents the tying of two signals together. One signal may be the anonymous result of a Boolean expression. In such cases, the destination signal, or output, changes as soon as there is change in the inputs. Signals that appear on the right hand side of the assignment are input signals. The synthesis tool will recognize, or infer, this usage by creating a logic, or combinatorial (aka combinational), circuit for the signals involved. This was the case for the assignments in Design 2.

If it’s a simple assignment of one signal to another, the two signals simply become the same signal. This was the case for Design 1.

Under clock control, the assignment represents the expected software notion of “updating” the destination signal. The synthesis tool will infer this from the use of a clock edge expression. The tool will create a register for the destination signal.

Earlier versions of ISE were able to complete the translation to a BIT file. For ISE 10.1, I needed to add an extra line in the UCF file:

NET "clk"  LOC = "M13" | IOSTANDARD = LVTTL ;
NET "din"  LOC = "F12" | IOSTANDARD = LVTTL ;
NET "dout"  LOC = "K12" | IOSTANDARD = LVTTL ;

NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;

The following shows how to put the assignment under clock control in VHDL:

-- This shows the code for creating a single-bit register.
--
-- To illustrate the proper functioning of the generated D-register,
--   we connect the clk input to a push button, and the din input to
--   a slide switch.
--
-- Some software (especially if it's old) will not synthesize
--   rising_edge(). For those development systems, the universal
--   (clk'event and clk = '1') is provided in a comment.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Register is
    Port ( clk : in std_logic;
           din : in std_logic;
           dout : out std_logic);
end Register1;

architecture Behavioral of Register is

begin

REG1 :
    process (clk)
    begin
        -- if clk'event and clk = '1' then
        if rising_edge(clk) then
            dout <= din;
        end if;
    end process;

end Behavioral;

The following shows how to put the assignment under clock control in Verilog. Notice that a signal that is assigned within an always block needs to be declared as a reg...

// This shows the code for creating a single-bit register.
//
// To illustrate the proper functioning of the generated D-register,
//   we connect the clk input to a push button, and the din input to
//   a slide switch.

module Register(
    input clk,
    input din,
    output reg dout
    );

    always @(posedge clk)
    begin
        dout <= din;
    end

endmodule

In both these cases, the register is updated when the clk signal changes from low (0) to high (1).