Design 4 – RS Latches

The RS latch is a “latch” because it is not synchronized to a clocking signal. There are separate R (reset to 0) and S (set to 1) inputs for forcing the state of the latch.

The RS latch is also known as a “flipflop” because it is not designed with a “transparent” operating mode. The R and S inputs are normally never both in the 1 state, so the RS latch appears to be a pure bistable device, just like a register.

Once again ISE 10.1 complains about one of the signals, S2. So here is the UCF file:

NET "R1"   LOC = "L13" | IOSTANDARD = LVTTL ;
NET "S1"   LOC = "L14" | IOSTANDARD = LVTTL ;
NET "Q1"   LOC = "P11" | IOSTANDARD = LVTTL ;
NET "N_Q1" LOC = "P12" | IOSTANDARD = LVTTL ;
NET "R2"   LOC = "M13" | IOSTANDARD = LVTTL ;
NET "S2"   LOC = "M14" | IOSTANDARD = LVTTL ;
NET "Q2"   LOC = "N14" | IOSTANDARD = LVTTL ;
NET "N_Q2" LOC = "L12" | IOSTANDARD = LVTTL ;

NET "S2" CLOCK_DEDICATED_ROUTE = FALSE;

Until now, the only real difference has been the more verbose style of VHDL over Verilog. The following pair of designs show more important differences – ones that impact the creation, debugging, and maintenance of code.

The first thing I want to point out is the addition of “internal” signals in the VHDL code. Unlike Verilog, an out port cannot be used internally to drive other logic. The deprecated buffer port has the same capability, but it has issues when connecting to out ports. And because out ports are used extensively, it’s too much of a hassle to use buffer.

The second thing to notice is the labelling of VHDL processes. Although Verilog allows labelling of always blocks with begin : <label> syntax, the Xilinx ISE software does not treat that label on an equal footing as the name of the FDCPE component. The result is that, under Verilog, always blocks are referenced by obscure component names.

Finally, VHDL does not need to be told that a signal is a reg or not. When reorganizing code, this makes it easy to move signal names into and out of processes or modules. In Verilog, a signal may be a reg or wire, but ironically a reg doesn’t necessarily mean a register.

For the following code, since we know that each pair of LED’s is driven from the same signal, we know that the ping-ponging between the two lights reflects the changing state of the RS Latch associated with them. We can also observe that after the LED’s switch to the correct state, pressing the same switch several times does not change the LED state.

First, we present the VHDL code…

-- RSLatches
--
-- Two versions of an RS latch are given.
--
-- The first version of the RS latch uses the RS latch embedded in an FPGA
--   flipflop register. The latch is accesed via the asynchronous clear and
--   preset inputs.
--
-- The second version is completely in VHDL. It does not generate normal
--   cross-coupled NAND or NOR gates. If you know digital circuits, take a
--   look, with the RTL viewer, at the logic constructed from the code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity RSLatches is
  port (
    -- RS Latch 1
    R1, S1:   in  std_logic;
    Q1, N_Q1: out std_logic;

    -- RS Latch 2
    R2, S2:   in  std_logic;
    Q2, N_Q2: out std_logic
  );
end RSLatches;

architecture Behavioral of RSLatches is
  signal iQ1, iQ2: std_logic;
begin

U_RSLATCH1 :
    FDCPE port map (
      C   => '0',
      CE  => '0',
      D   => '0',
      CLR => R1,
      PRE => S1,
      Q   => iQ1
    );

    Q1   <= iQ1;
    N_Q1 <= not iQ1;

U_RSLATCH2 :
    process (R2, S2)
    begin
      if    R2 = '1' then
        iQ2 <= '0';
      elsif S2 = '1' then
        iQ2 <= '1';
      end if;
    end process;

    Q2   <= iQ2;
    N_Q2 <= not iQ2;

end Behavioral;

And then we present the Verilog code...

// RSLatches
//
// Two versions of an RS latch are given.
//
// The first version of the RS latch uses the RS latch embedded in an FPGA
//   flipflop register. The latch is accesed via the asynchronous clear and
//   preset inputs.
//
// The second version is completely in Verilog. It does not generate normal
//   cross-coupled NAND or NOR gates. If you know digital circuits, take a
//   look, with the RTL viewer, at the logic constructed from the code.

module RSLatches (
    // RS Latch 1
    input R1, S1,
    output Q1, N_Q1,

    // RS Latch 2
    input R2, S2,
    output reg Q2,
    output N_Q2
    );

    FDCPE U_RSLATCH1 (
      .C(0),
      .CE(0),
      .D(0),
      .CLR(R1),
      .PRE(S1),
      .Q(Q1)
    );

    assign N_Q1 = ~Q1;

    // RS Latch 2

    always @(posedge R2 or posedge S2)
    begin
      if      (R2) Q2 <= 0;
      else if (S2) Q2 <= 1;
    end

    assign N_Q2 = ~Q2;

endmodule