tk's bits

Sensitivity lists

In VHDL, the list of names after the process keyword is the sensitivity list. The sensitivity list is processed by software simulators, which are normally used to verify designs before they are embedded in real hardware. In fact, VHDL and Verilog were designed as simulation languages, and have been forced, in a Procrustean manner, to work as direct design languages. When ISE complains about the sensitivity list, it is warning you that a simulator might not faithfully reproduce the hardware behavior.

The rules for “faithful” sensitivity lists in VHDL are fairly simple. Let’s look at an example:

process (clk, A, start_value)
begin
  if A = '1' then
    count <= start_value;
  else if rising_edge(clk) then
    if B = '1' then
      count <= count + 1;
    end if;
  end if;
end process;

I tend to think of the code block between rising_edge(clk) and the final end if as being "conditioned" by a clock signal. Notice that, from this code block, only the clock signal, clk, is listed in the sensitivity list. Outside this "clock conditioned" code, all signals being tested or used to generate a value are listed - that means A and start_value, but not B or count.